Coordinated concurrent memory accesses on a reconfigurable multimedia accelerator

Reconfigurable fabrics are designed by tiling operators and memory banks. In the context of system on chip, the inclusion of multiple local memories is critical for algorithmic performance, as they provide concurrent data accesses for configured compute processes. This paper considers a practical case where internal fabric buses and connectivity give a shared memory characteristic to the architecture. This relies on static reconfigurability and high-level programming techniques to render automated memory access scheduling feasible in a deterministic manner. A complete flow has been developed starting from the programming model down to micro-code enabling task synchronization on memory resources. Compile time analysis is achieved by observing the sequence of operations in the concurrent processes, and by synthesizing a controller program to support the best schedule of operations favoring high throughput. The hardware target is a reconfigurable fabric designed at STMicroelectronics in 65 nm. This hardware/software solution is scalable, flexible and provides high throughput on shared memory.