Capturing and optimizing the interactions between prefetching and cache line turnoff

While numerous prior studies focused on performance and energy optimizations for caches, their interactions have received much less attention. This is unfortunate since in general the performance oriented techniques influence energy behavior of the cache, and the energy oriented techniques usually increase program execution cycles. The overall energy and performance behavior of caches in embedded systems when multiple techniques co-exist remains an open research problem. This paper first studies this interaction and demonstrates how performance and energy optimizations can affect each other. We then propose three optimization schemes that turn-off cache lines in a prefetching-sensitive manner. Specifically, these schemes treat prefetched cache lines differently from the lines brought to the cache in a normal way (i.e., through a load operation) in turning off the cache lines. Our experiments with five randomly selected codes from the SPEC2000 suite indicate that the proposed approaches save significant leakage energy. Our results also show that the performance degradations incurred by the proposed approaches are very small.