Integer-pixel motion estimation H.264/AVC accelerator architecture with optimal memory management

This paper presents an improved accelerator core for H.264/AVC video-coding motion estimation. The proposed hardware architecture meets the integer-pixel, full-search block-matching algorithm requirements with an optimal memory management and an effective data-path. Performance characteristics like low latency, high processing speed and efficiency near 100% are achieved without a high control overhead. The core calculates the 41 best motion vectors using a pipeline process. It is composed of a systolic 16 × 16 processor elements array, a sum of absolute differences adder tree and a Lagrangian rate/distortion cost optimizer. Implementation results based on FPGA devices in a system on chip (SoC) structure using VHDL are included.