Article ID Journal Published Year Pages File Type
463098 Microprocessors and Microsystems 2012 9 Pages PDF
Abstract

This paper proposes techniques for face detection using Haar-like features as weak classifiers and gives the implementation details for an FPGA development board. We analyze and discuss the relation between the system computation cost and selection of the image scaling factor. Based on the empirical results of our previous work, we give a new method to select the stop threshold for the image reduction process, which reduces the total computation by half. We present and implement an improved integral image pipeline calculation design. We also provide a color image output mode to let our system enjoy more human-oriented design. Test results show that the system achieves real-time face detection speed (100fps) and a high face detection rate (87.2%) for an SVGA (600 × 800) video source. The low power consumption (3.5 W) is another advantage over previous work.

Related Topics
Physical Sciences and Engineering Computer Science Computer Networks and Communications
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