Dynamic power management of DRAM using accessed physical addresses

Power management is an important part of handheld systems such as PDAs, smartphones, and other battery operated digital devices. A handheld system can transition the nodes of a DRAM to low power state to reduce energy consumption. We propose an efficient method for dynamic power management (DPM) of DRAM based on accessed physical addresses. The proposed method also reduces the number of times resynchronization is done. There is no need to collect scattered pages, as in conventional page clustering mechanisms that focus on virtual memory (VM). Simulation result shows that the proposed method reduces Energy ∗ Delay Product by as much as 75% when compared to DRAMs with no DPM.