Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
463184 | Microprocessors and Microsystems | 2008 | 13 Pages |
Abstract
This paper presents a design methodology for a hybrid Hardware-in-the-Loop (HIL) tester tool, based on both discrete event system theory, given by timed automata, and continuous systems theory, given by difference equations. It is implemented using an FPGA platform that guarantees speed enhancement, time accuracy and extensibility with no performance loss. We have focused on the implementation of a discrete event system, specifically timed automata into FPGA, and we have linked them with continuous systems implemented as filters in fixed point arithmetic. The paper shows a methodology, which employs widely used tools (Matlab, UPPAAL) as a user interface, and which implements the FPGA based tester tool.
Related Topics
Physical Sciences and Engineering
Computer Science
Computer Networks and Communications
Authors
Jan Krákora, Zdeněk Hanzálek,