Experiences with a FPGA-based Reed/Solomon-encoding coprocessor

In this paper we present an implementation of a Reed/Solomon (R/S)-coprocessor to be used on a hybrid computing system, which combines general purpose CPUs with FPGAs. The coprocessor accelerates the encoding of user data to be stored block-wise on a distributed, failure-tolerant storage system. We document design constraints and their impact on the resulting architecture. Measurements are presented to characterize the performance of the coprocessor in terms of computational bandwidth, latency, and the hardware–software interaction. For comparison, software-based R/S-encoding implementations are presented and evaluated as well. The two variants of the FPGA-based coprocessors are compared to each other with respect to their fitting to a distributed storage application.