GDI based full adders for energy efficient arithmetic applications

Addition is a vital arithmetic operation and acts as a building block for synthesizing all other operations. A high-performance adder is one of the key components in the design of application specific integrated circuits. In this paper, three low power full adders are designed with full swing AND, OR and XOR gates to alleviate threshold voltage problem which is commonly encountered in Gate Diffusion Input (GDI) logic. This problem usually does not allow the full adder circuits to operate without additional inverters. However, the three full adders are successfully realized using full swing gates with the significant improvement in their performance. The performance of the proposed designs is compared with the other full adder designs, namely CMOS, CPL, hybrid and GDI through SPICE simulations using 45 nm technology models. Simulation results reveal that proposed designs have lower energy consumption among all the conventional designs taken for comparison.