Efficient FPGA Implementation of the RC4 Stream Cipher using Block RAM and Pipelining

RC4 is a popular stream cipher, which is widely used in many security protocols and standards due to its speed and flexibility. Several hardware implementations were previously suggested in the literature with the goal of improving the performance, area, or both. In this paper, a new hardware implementation of the RC4 algorithm using FPGA is proposed. The main idea of this design is the use of a dual-port block RAM in the FPGA in order to better utilize the available logic and memory resources. Combined with a new pipelined hardware implementation, the new design achieves better performance. The design is described using Verilog HDL and synthesized and implemented using Xilinx ISE suite for different FPGA devices. Synthesis results show that the proposed design achieves higher efficiency than previous implementations by reducing area while maintaining a good throughput/LUT ratio. The proposed design is also more efficient in terms of power consumption.