Low-Power Universal Edge Tracer Architecture using Accuracy-Controlled Resource Reallocation for Event-Driven Sensing Applications

The low-power memory tracer architecture for sense data acquisition is proposed. The hardware pre-processor based on the proposed sense data tracer enables the low-power sense data analysis in,a noisy environment. The sensed signals are tagged with the edge phases, threshold level, and elapsed timing distance between previous signal edges. The incoming sense data analysis is delayed, and its raw data is reallocated into the tracer memory. The traced sensed data is analyzed by the allocated event pattern- matcher in the silent background mode without any CPU assistance. The proposed method and hardware architecture enable an accurate original sense data reconstruction in the slow processor clock frequency. Newly designed building blocks are integrated into previously designed sensor processors for 3DTV active shutter glasses. The experimental result shows an additional power reduction to about 25% of our previous work by allowing a small amount of error in the original sense data reconstruction. This paper describes the systems’ architecture and details of the proposed memory tracer in addition identifying the key concepts and functions.