A Packet Switch Scheduler based on 2DRR for High-Throughput

Recently, the need of the high speed packet switch is increased. The basic 2DRR scheduling algorithm provides high throughput, fair access and simple working on a packet switch. However, few input and output node could not be permissioned in some timeslots. It occurs decreasing throughput and some transmission delay. This paper proposes a new packet switch scheduling algorithm. The proposed scheduling algorithm provides higher throughput and low delay. The effectiveness of the proposed algorithm is shown through simulation studies.