An Efficient 256-Tap Parallel FIR Digital Filter Implementation Using Distributed Arithmetic Architecture

This paper discusses FPGA implementation of Finite Impulse Response (FIR) filters using Distributed Arithmetic (DA) which substitute multiply and accumulate operations with a series of Look-Up-Table (LUT) accesses. Parallel FIR digital filter can be used either for high speed or low-power applications. The distributed arithmetic provides a multiplication-free method for calculating inner products of fixed-point data, based on table lookups of pre calculated partial products. The implementation results are provided to demonstrate a high-speed and low power proposed architecture. The proposed filter is implemented in very high speed integrated circuit hardware description language (VHDL) and verified via simulation. The proposed method offers average reductions of 60% in the number of LUT, 40% reduction in occupied slices and 50% reduction in the number gates for parallel FIR filter implementation.