FPGA Based Denoising Method with T-Model Mask Architecture Design for Removal of Noises in Images

The process of image acquisition, conversion of images into different form and transmission of images for various applications the originality of capture images are affected by different noises. The various techniques are proposed for removing noises in digital images. The main problem of these techniques is degrading the image information. Hence, in this paper, an efficient VLSI (Very Large Scale Integrated Circuits) implementation of Trimmed median filter algorithm with T-Model mask technique is used for removal of impulse noise is proposed. The proposed algorithm removes the noise presented in digital images without degrading the image information. The VLSI architecture implemented on FPGA (Field Programmable Gate Array) by pipelining with parallel processing in order to improve the performance of filtering process and reduces the delay. The performance of proposed algorithm is compared with different denoising methods and implemented on FPGA.