Synthesis and Realization of N-bit Reversible Register File Used in Bus Organization of Processor Architecture

In a processor architecture, the beauty of bus organization lies on the easy transferring of data or word from one register to another. Register file consisting of many storage locations is the heart of that bus organization as well as the processor. Energy dissipation per device per operation cannot be reduced further than KTln2, rather it is possible only if the computation the operation is done based on reversible principle due to fundamental thermodynamic reasons. In this paper, we have realized reversible register file to show data transfer in the bus and analyzed the operation in terms of an algorithm. While approaching for the design we have also synthesized a novel reversible decoder in terms of an algorithm and many lemmas. As efficient design methodology is mandatory for increasing the speed of operation, reducing complexity and size of bus organization, we have analyzed such a reversible model which allows the processor not to face overheads in terms of cost, delay and garbage.