Comparative Design and Analysis of Mesh, Torus and Ring NoC

The research article presents the simulation and FPGA synthesis of mesh, torus and ring Network on Chip (NoC). The network is based on the Multiprocessor System on Chip (MPSoC) structure for a network cluster of 256 nodes. The paper focuses on the comparative analysis based on hardware design parameters, memory utilization and timing parameters such as minimum and maximum period, frequency support. The interprocess communication among nodes in verified using Virtex-5 FPGA with an arbitration logic. The designs are developed in Xilinx ISE 14.2 and simulated in Modelsim 10.1b with the help of VHDL programming language. Network topological structures help for on chip intercommunication, routing, switching, flow control, queuing, scheduling and to communicate among different networks.