Signal Processing using FPGA Structures

This work describes a Virtex-II implementation of a digital signal processing module for filtering data signals. The aim of any filtering process is to have a clean signal for analysis and interpretation.A synthesized noisy signal (with known noise) will be used as input to test the modules implemented on FPGA. The Xilinx System Generator Environment will be used in simulation and discrete wavelet transform based filter synthesis, respectively for hardware co-simulation. In order to evaluate the filtering procedure signal to noise ratio and RMS error are measured and compared at different noise levels and different analyzing functions (wavelets).