Real-time Architecture and FPGA Implementation of Adaptive General Spectral Substraction Method

Spectral Subtraction (SS) method is one method for speech enhancement or noise cancellation. There are many variations of SS method, one of them is Adaptive General Spectral Subtraction (AGSS). In this paper, we implement the noise cancellation method in FPGA as hardware to perform real-time speech enhancement. The hardware implementation consists of FIFO block, window block, FFT/IFFT block, noise cancellation block, half overlap block, and hardware buffer block. Our hardware design utilizes 5086 logic elements with additional 2.18kB memory in total. Latency of the hardware is 2.48 μs in 217 clock cycles with 87.54 MHz maximum frequency. The latency is less than the sampling period which is 125 μs, so it can perform real-time speech enhancement, as have been tested in Altera DE2-70 board.