FPGA Implementation of Fixed-point Divider Using Pre-computed Values

In this paper, we propose a divider block architecture using pre-computed values. At the first stage, the input is scaled so that the denominator, D, has value between 0.5 and 1. Then the block takes a pre-computed value corresponding to 1/D and multiplies it with the nominator. In order to save utilized memory bits, we take only several bits from D. In the end, we compare synthesis result of our divider block with several divider block implementations. The result shows that our divider block gives the smallest total logic elements and the shortest latency among the compared blocks.