A CMOS current mode four quadrant analog multiplier free from mobility reduction

This paper describes a simple technique for reducing the mobility degradation effect. A current mode squarer circuit and a four quadrant analog multiplier are designed using this technique. The proposed circuits are designed and simulated using the ELDO simulator in 0.18 µm CMOS technology with a power supply of ±0.75 V. The simulation results of analog multiplier for an input range of ±10 µA that demonstrates a −3 dB bandwidth of 300 MHz, a 0.15 mW of maximum power consumption, a low nonlinearity error of 1.1% and a THD of 0.8% in 1 MHz. Monte Carlo simulation of the proposed multiplier is analysed to verify the robustness of the circuit versus the technological process.