The design and analysis of dual control voltages delay cell for low power and wide tuning range ring oscillators in 65 nm CMOS technology for CDR applications

In this paper three delay cell structures used in four-stage ring oscillator are evaluated. In the first structure, the control voltage is employed to the gate of PMOS transistors which are inserted in series with the input PMOS transistors. In this case the minimum power dissipation is gained. Since the control voltage is injected to the PMOS transistors parallel with input transistors, the better tuning range in higher frequency and lower phase noise is achieved. In order to make a tradeoff between the tuning range, phase noise and power dissipation, the PMOS transistors activated with the control voltage are applied to the oscillator in both the series and parallel paths. In improved structure, the oscillator works in 2.65-13.93 GHz under 1 V supply voltage in 65 nm CMOS technology. The phase noise is −94.33 dBc/Hz at 1 MHz offset from 3.7 GHz center frequency, while the power dissipation is 328.6 μW and the chip area is 139.5 µm2.