A 5Â Gbps serial link pre-emphasis transmitter with a novel-designed register based multiplexer

A serial link transmitter with 4-tap pre-emphasis is presented in this manuscript. The system consists of two 5:1 multiplexers, a 2:1CML multiplexer, and a driver with 4-tap pre-emphasis. A new 5:1 multiplexer structure is proposed to prevent sampling on the data edge, which shows a lower power consumption and chip size. Implement in standard 180 nm CMOS 1P6M process with 1.8 V power supply, the newly designed transmitter can be able to work with bit error rate (BER) as 10−14. The transmitter output jitter is 0.09UI while the amplitude can reach from 540 mV to 750 mV.