Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
4956648 | Microprocessors and Microsystems | 2017 | 15 Pages |
Abstract
For a 4MB 4 way set associative L2 cache, experimental analysis shows 66% reduction in static energy with 29% gain in Energy Delay Product (EDP) for first strategy; for the second policy, static power is reduced by 59% with 27% savings in EDP. Finally, last policy saves 65% in static power and 30% in EDP with minimal performance penalty.
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Authors
Shounak Chakraborty, Hemangee K. Kapoor,