Design of a reversible floating-point square root using modified non-restoring algorithm

In this work, a reversible single precision floating-point square root is proposed using modified non-restoring algorithm. To our knowledge, this is the first work proposed for floating-point square root using reversible logic. The main block involved in the implementation of reversible square root using modified non-restoring technique is Reversible Controlled-Subtract-Multiplex. Further, optimized Reversible Controlled-Subtract-Multiplex blocks are introduced in order to minimize the number of reversible gates used, number of constant inputs used, number of garbage outputs produced as well as the quantum cost. The proposed reversible single precision floating-point square root is realized using an 8-bit reversible adder, an 8-bit and a 25-bit reversible shift register, 12-bit reversible unsigned square root, 6-bit reversible unsigned square root, 4-bit reversible unsigned square root, 3-bit reversible unsigned square root and ten 1-bit reversible unsigned square root units.