Article ID Journal Published Year Pages File Type
4956772 Microprocessors and Microsystems 2017 25 Pages PDF
Abstract
In this paper, we propose a novel architecture for inter-FPGA collision management in the Network-on-Chip partitioned on multi-FPGAs. The structure ensures to efficiently share the external link between several routers with a minimum number of collisions and inter-FPGA bottlenecks. The proposed architecture is easily placed between the Network-on-Chip and the external protocol. The collision management architecture is based on the BackOff algorithm used in Wi-Fi communications and adapted to FPGA platforms. This algorithm balances accesses among all the routers connected with the inter-board interfacing, thereby avoiding collisions. We compare this structure with traditional techniques using experimental and theoretical results. The novel inter-FPGA architecture for the Network-on-Chip based on the BackOff algorithm achieves lower latency with fewer resources compared to other solutions.
Related Topics
Physical Sciences and Engineering Computer Science Computer Networks and Communications
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