Empirical results on parity-based soft error detection with software-based retry

•An error detection-based fault-tolerance approach is proposed for digital circuits.•The approach is based on local error detection and external retry.•Synthesis results show an area overhead saving of 29% up to 36% compared to LTMR.

Local triple modular redundancy (LTMR) is often the first choice to harden the FFs of a flash-based FPGA application against radiation-induced bitflips in space, but LTMR leads to an area overhead of roughly 300%. To cope with this significant overhead, we propose an error detection based approach. In this work, we compare parity-based error detection with software-based retry, and LTMR on a reference architecture regarding maximum frequency, area overhead and processing time. Our results show that our solution based on parity-based error-detection saves from 29% up to 36% of the area overhead caused by LTMR.