Article ID Journal Published Year Pages File Type
4956843 Microprocessors and Microsystems 2016 7 Pages PDF
Abstract
In order to improve the efficiency of modular multiplication algorithm for FPGA implementation on the prime field modular, an efficient scheme is proposed to accomplish 256 × 256 bits modular multiplication algorithm. The embedded IP cores of Xilinx FPGA are efficiently utilized to design 512-bit addition and 256 × 256 bits multiplier. Moreover, the above modules are used to complete Montgomery modular multiplication algorithm. Compared with traditional implementation method, almost 50% running efficiency is improved in our scheme, which has important value to implement complicated cryptographic processor in hardware environment.
Related Topics
Physical Sciences and Engineering Computer Science Computer Networks and Communications
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