Efficient power analysis approach and its application to system-on-chip design

This paper demonstrates power estimation technique using input patterns with the predefined statistical characteristics that helps to analyze the average power consumption of the different intellectual-property (IP) cores and the interconnects/buses in SoC design. Genetic algorithm (GA) is implemented for the generation of sequences of input signals during the power estimation procedure. The GA concurrently optimizes the input signal characteristics that influence the final solution of the pattern. Then, a Monte-Carlo zero-delay simulation is performed for individual IP core and bus at high-level. By the simple addition of these cores/buses, power is predicted by a novel macro-model function. The meta-modeling technique is adopted to improve accuracy of the samples of realistic data for the quality of results. In experiments with the IP-based SoC system, the average error is estimated 11.42%.