| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 4956882 | Microprocessors and Microsystems | 2016 | 4 Pages |
Abstract
This paper proposes some corrections and comments to the BCD multiplier presented in the paper “Fast architecture for decimal digit multiplication”, published in the Journal of Microprocessors and Microsystems (Volume 39, 2015, issues 4-5, pages 296-301). Some corrections are first proposed to the presented binary multiplier, while the discussion is later extended to some issues that have been found regarding the binary-to-BCD converter.
Keywords
Related Topics
Physical Sciences and Engineering
Computer Science
Computer Networks and Communications
Authors
E. Castillo, A. Lloris, A. GarcÃa, L. Parrilla, D.P. Morales,