A Project of Compiler for a Processor with Programmable Accelerator

In the following work, a project for compiler that maps program loops onto a processor with programmable accelerator is presented. The processor with programmable architecture could be a system on a chip containing regular computational cores as well as a programmable circuit. A classification of loops according to information dependencies is suggested. For each loop class, the possibility and method for automatic organization of hardware support with an FPGA are examined. The compiler under study differs from the regular ones for the presence of a converter from C to the hardware description language as well as a driver library for data transfer between a CPU and accelerator.