Improved Architecture for Tag Matching in Cache Memory Coded with Error Correcting Codes

Cache memories serve as accelerators to improve the performance of modern microprocessors. Caches are vulnerable to soft errors because of technology scaling. So it is important to provide protection mechanisms against soft errors. Tag comparison is critical in cache memories to keep data integrity and high hit ratio. Error correcting codes (ECC) are used to enhance reliability of memory structures. The previous solution for cache access is to decode each cache way to detect and correct errors. In the proposed architecture ECC delay is moved to the non-critical path of the process by directly comparing the retrieved tag with the incoming new information which is encoded as well, thus reducing circuit complexity. For the efficient computation of hamming distance, butterfly weight accumulator is proposed to reduce latency and complexity further. The proposed architecture checks whether the incoming data matches the stored data. The proposed architecture reduces the latency and hardware complexity compared with the most recent implementation.