Influence of pre-polishing process on site flatness values of polished wafers

The preparation of semiconductor silicon polished wafer is a multi-stage manufacturing process. This paper analyzed the influence of polished wafers' SFQR (Site flatness front least square range) values with different pre-polishing process. In this study, the pre-polishing processes included dual-side lapping & etching, dual-side grinding and back-side polishing. Among them, the etching process was divided into caustic etching and acid etching with different removal amount and different rotation speed. The experimental results show that different pre-polishing processes have significant effects on SFQR values of polished wafers. Caustic etching, dual-side grinding and back-side polishing are more suitable for polished wafer's SFQR, while the center area of acid etching wafers show worse polished wafer's SFQR due to the etching mechanism.