Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
5010385 | Solid-State Electronics | 2017 | 9 Pages |
Abstract
A V-band power amplifier in a bulk 65Â nm CMOS technology with a peak gain 14.5Â dB and 3-dB bandwidth of 28.8Â GHz (50.8-79.6Â GHz) is presented. The techniques to boost bandwidth and power efficiency are presented. In addition, the design of dummy filling to satisfy manufacturing density requirements while having negligible effects on performances is discussed in details. The PA features a three stage transformer coupled differential architecture with integrated input and output baluns on-chip. The PA achieves a measured saturated output power of 15.1Â dBm and output 1Â dB compression power of 12.9Â dBm at 65Â GHz. The peak power-added efficiency is 18.9%. The entire PA occupies area of 0.31Â mm2, while consuming 150Â mW from a 1.25Â V supply.
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Physical Sciences and Engineering
Engineering
Electrical and Electronic Engineering
Authors
Yu-Ting Chang, Yu Ye, Hongtao Xu, Calvin Domier, N.C. Jr, Q. Jane Gu,