Novel Power Consumption Reduction Strategy (PCRS) Using Mixed-VTH Cells for Optimizing the Cells on Critical Paths for Low-power SOC

In this paper, a novel power consumption reduction strategy (PCRS) using mixed-VTH (MVT) cells with unbalanced timing arcs (UTA) for low-voltage/low-power SOC applications is presented. Via selecting the fastest timing arc for the critical path- MVT cell variant selection (CVS) criteria and adopting cell assignment algorithm (CAA) to integrate MVT cells out of the HVT/LVT/MVT pool for the circuit optimization flow, the PCRS provides a low-voltage/low-power SOC design as indicated in a 16-bit multiplier with 5584 cells, using a 90 nm CMOS technology at 1 V under the tightest delay constraint with a 5.15% reduction in power consumption as compared to the one optimized by the CBLPRP technique.