Novel hardware processing unit for dynamic on-line entropy estimation of discrete time information

This paper presents a novel and generic hardware processing unit that estimates the information entropy in a dynamic and on-line fashion with a simple architecture that can be easily scaled. This architecture does not require precomputations, change of domain at the input signal, or complex schemes of computation. Results show that the proposed FPGA implementation of the dynamic entropy estimator is highly efficient as a stand-alone system. Speed performance of the system is 3 orders of magnitude higher than its implementation counterpart in software with a maximum error of 1.5%. Compared with other hardware structures, the proposed architecture is able to process twice the information than a LUT-based entropy estimator during a time unit. Results also show that the proposed dynamic hardware processing unit is highly accurate carrying out standard tasks such as computing the information content in a discrete data set, or nonstandard tasks as detecting failures in induction motors.