Analysis and simulation of continuous-time digital signal processors

Digital signal processors operating in continuous time are analyzed. We demonstrate, through analytical and simulation studies, that by operating without a sampling clock the in-band quantization error power is reduced compared to conventional discrete-time systems. We present an equivalence that facilitates the study of continuous-time digital signal processors and we explore in detail the case of single sinusoid inputs as well as inputs with a Gaussian distribution. The in-band quantization error power is shown to be lower by up to 25dB for an 88-bit system, compared to a classical, sampled one with the same resolution.