Discrete cosine and sine transforms—regular algorithms and pipeline architectures

In this paper, regular fast algorithms for discrete cosine transform (DCT) and discrete sine transform (DST) of types II–IV are proposed and mapped onto pipeline architectures. The algorithms are based on the factorization of transform matrices described earlier by Wang. The regular structures of the algorithms are advantageous when mapping them onto hardware although such algorithms do not reach the theoretical lower bound on multiplicative complexity. Instead, the algorithms lend themselves for vertical mapping resulting in area-efficient pipeline structures. A unified pipeline architecture supporting both the DCT-II and its inverse is implemented with data path synthesis for proving the feasibility and estimating the performance. The latency of an ASIC implementation is 94 cycles while operating at 250 MHz frequency.