Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
6879462 | AEU - International Journal of Electronics and Communications | 2018 | 21 Pages |
Abstract
This paper presents a model and a novel architecture of a low-power pipelined analog-to-digital converter (ADC) without using front-end Sample and Hold Amplifier (SHA) stage. The modeling of all ADC building blocks along with their non-ideal effects have been implemented in MATLAB SIMULINK environment and the main transistor level circuits have been implemented in H-SPICE environment using 180-nm TSMC CMOS technology. The maximum DNL and INL amounts are equal to ±0.9 LSB and ±2.3 LSB, respectively. Applying a 33.1â¯MHz with 1.4â¯Vp-p (â6dBFS) input signal, achieved SNDR is 61â¯dB resulting in 9.8 Bits ENOB with total power consumption of 42â¯mW.
Related Topics
Physical Sciences and Engineering
Computer Science
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Authors
H. Imanpoor, M. Mehranpouy, P. Torkzadeh, A. Jannesari,