Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
6879478 | AEU - International Journal of Electronics and Communications | 2018 | 9 Pages |
Abstract
This paper presents a 5.7-6.0â¯GHz Phase-Locked Loop (PLL) design using a 130â¯nm 2P6M CMOS process. We propose to suppress reference spur through reducing the current mismatch in charge pump (CP), controlling the delay time in phase frequency detector (PFD), and using a smaller VCO gain (KVCO). With a reference frequency of 32.768â¯MHz, chip measurement results show that the frequency tuning range is 5.7-6.0â¯GHz, the reference spur is â68â¯dBc, the phase noise levels are â109â¯dBc/Hz and â135â¯dBc/Hz at 1â¯MHz and 10â¯MHz offset respectively for 5.835â¯GHz. Compared with existing designs in the literature, this work's reference spur is improved by at least 17% and its phase noise is the lowest. Under a 1.5â¯V supply voltage, the power dissipation with an output buffer of the PLL is 12â¯mW.
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Physical Sciences and Engineering
Computer Science
Computer Networks and Communications
Authors
Xiaoqiang Li, Jingwei Zhang, Yuanzhi Zhang, Wenshen Wang, Huimin Liu, Chao Lu,