Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
6883435 | Computers & Electrical Engineering | 2018 | 22 Pages |
Abstract
To fully exploit the massive parallelism of many-core on a chip, this work tackles the problem of mapping large-scale applications onto heterogeneous networks-on-chip (NoCs) while minimizing hotspots. A task-resource co-optimization framework is proposed which configures the on-chip communication infrastructure and maps the applications simultaneously and coherently, aiming to minimize the peak energy under the constraints of computation power, communication capacity, and total cost budget of on-chip resources. The problem is first formulated into a linear programming model to search for optimal solution. A heuristic is further developed for fast design space exploration at design-time and run-time in large-scale NoCs. Extensive simulations are carried out under real-world benchmarks and randomly generated task graphs to demonstrate the effectiveness and efficiency of the proposed schemes. Real system simulations show the significant improvement (30-200%) in NoCs latency and throughput compared to the state-of-the-art minimum-path approach because of the diminishing hotspots and balanced load distribution.
Related Topics
Physical Sciences and Engineering
Computer Science
Computer Networks and Communications
Authors
Md Farhadur Reza, Dan Zhao, Hongyi Wu, Magdy Bayoumi,