CMOS design of computational current-mode static and dynamic functions based on analog translinear cell

In this paper, the systematic realizations of some low-power nonlinear current-mode computational/configurable analog blocks (CABs) are presented. These CABs are based on a most demanded novel precise analysis and removal method of complete non-idealities of CMOS transistors. The proposed CAB architecture consists of a novel MOS translinear cell (MTC) that includes two overlapping up-down loops using MOS translinear principle (MTLP) in sub-threshold region. The proposed design with properly signal/bias injection scheme to MTC via NMOS-PMOS arrays is able to produce some current-mode nonlinear static and dynamic functions. Those are as vector summation, cube/third power, true RMS to DC converter and first-order low-pass log-domain filter. The designed functions are simulated by HSPICE simulator in TSMC 0.18 µm (level-49 parameters) CMOS technology. Pre and post-layout simulation results both plus Monte Carlo analysis are compared with other artworks that verified the functionality, flexibility and superiority of the proposed CABs.