Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
6883457 | Computers & Electrical Engineering | 2018 | 16 Pages |
Abstract
In this paper, an efficient sub-word parallelism (SWP)-enabled Reduced instruction-set Computer (RISC) architecture is proposed. The proposed architecture can perform efficiently for both conventional and multimedia-oriented applications. Speed-up for multimedia applications is achieved by adding the customized SWP instructions in RISC processor core. Rather than operating on a single data, customized instructions perform parallel computations on multiple pixels, packed in word-size registers. The sub-word-sizes in SWP instructions are selected, based upon the pixel sizes (8, 10, 12, 16-bit) in modern multimedia applications. The SWP-RISC processor is designed and implemented on two different CMOS technology nodes (90Â nm and 45Â nm). The performance of processor is characterized for different multimedia applications and compared with the state-of-the-art TMS320C64X processor.
Keywords
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Physical Sciences and Engineering
Computer Science
Computer Networks and Communications
Authors
Shafqat Khan, Muhammad Rashid, Faraz Javaid,