High speed and efficient area optimal ate pairing processor implementation over BN and BLS12 curves on FPGA

In this paper, a novel high speed and efficient area optimal Ate pairing processor implementation over Barreto-Naehrig (BN) and Barreto-Lynn-Scott (BLS12) curves on field-programmable gate array (FPGA) is proposed. The optimal Ate pairing proposed design, based on two steps: Miller loop and final exponentiation, is specifically optimized for FPGA platforms. The Miller Loop and Final Exponentiation algorithms are optimized and modified for careful scheduling to avoid data dependency and to decrease the number of loops and number of temporary variables required for final exponentiation. Furthermore, suitable multiplier combining Toom-Cook and Karatsuba algorithms is proposed to execute the arithmetical computations needed in pairing architecture processor over Fp.Therefore, an enhancement in terms of pairing computation speed-up and memory resources capacity management is achieved. In this paper, we select the new pairing parameters, especially that has to be used to ensure the 128-bit security level [1]. The proposed optimal Ate pairing architecture at 128 bits security level has been implemented on Xilinx FPGA Virtex6. Our processor implemented over BN curves achieves the highest reported speed together with the best reported area-time performance on Virtex6 (0.35 ms at 225 Mhz). Finally, for BN-446 and BN-638, the pairing proposed processor performances are estimated.