A new design and implementation of hardware accelerator for line detection

Linear detection algorithms require a series of sequential and complex process that needs high-performance processors to reduce computing time when the software is implemented. In this paper, we design a linear detection hardware accelerator with parallel computing capability through our proposed pipelined multiprocessor system-on-a-chip (SoC) design methodology; it contains an upper pipelined controller that controls the operation of the underlying Canny edge detection module and the Hough transform module. That is, we first use the edge detection module to get the edge information, and then use Hough transform to improve the accuracy of linear detection results. Finally, the pipeline control is adopted to enhance the effectiveness of the module. Based on the Canny process and the Gaussian blurring method, this study can reduce the false detection caused by noise, and decrease the number of operations and resource usage without affecting the straight line detection. Compared with Xu and Chen [14] [21] [34] [35], the proposed method can reduce 84% and 74% of the circuit resources, respectively. The hardware function circuit generated from our methodology has a good decentralized architecture and scalability, and it is easier to use in all kinds of embedded systems.