FastSpice circuit partitioning to compute DC operating points preserving Spice-like simulators accuracy

FastSpice techniques are considered in this paper and in particular partitioning methods that split a large circuit in a set of smaller sub-circuits to quickly and accurately compute a dc solution. Each sub-circuit contributes to a set of Jacobian matrices with reduced dimensions that are more efficiently LU-factorised during the iterations of the solving methods. As a matter of fact, the numerical effort required by factorisation is a non linear (polynomial) function of the matrix dimension. We describe the use of voltage and current probes that can be inserted to “virtually” tear nodes and branches of the original circuit to further improve circuit splitting. The proposed techniques do not alter the accuracy of the simulation and thus we obtain FastSpice performances while keeping Spice accuracy. This can be a key issue in simulating circuits designed with deep-submicron technologies. Simulation performances of the proposed approach are compared with those of modern commercial full-chip FastSpice and Spice-like simulators.