Novel power U-MOSFET with SIPOS pillars

In this paper, a novel vertical U-MOSFET using Semi-Insulating Poly-crystalline Silicon pillars (SIPOS) is presented. The proposed SIPOS UMOS combines two benefits of majority carrier accumulation and electric field modulation to improve the trade-off between the breakdown voltage (BV) and the specific-on-resistance (Ron,sp) of the device. In the off-state, the reshaping effect of the SIPOS pillars enhances the vertical electric field strength and weakens the peak electric field at the bottom of the gate trench, thereby increasing the BV. In addition, a highly doped N-drift is allowed for SIPOS UMOS because of the enhanced depletion by the SIPOS pillars, leading to a low Ron,sp. In the on-state, the Ron,sp is further reduced by the majority carrier accumulation layer that formed in the drift region. The results carried by TCAD simulation show that the BV of SIPOS UMOS is increased by 12.5% and 36.2% compared with the conventional superjunction UMOS and the UMOS without the SIPOS pillars in the same drift length, respectively. Moreover, the Ron,sp of SIPOS UMOS is reduced by 31.3% and 85.8%, respectively.