Optimization of nanometer bulk junctionless Trigate FET using gate and isolation dielectric engineering

In this paper, the performance of bulk junctionless trigate FET is enhanced by optimizing the (WFISO) GateISO work function (GateISO is the portion of the gate above isolation dielectric), isolation dielectric permittivity (KISO), and GateFIN dielectric (GateFIN is the portion of the gate covering the fin) permittivity(KFIN). SiO2, Si3N4 and HfO2 dielectrics with gate work functions in the range of 4-5.6 eV are used in this study. The performance is enhanced in terms of ION, IOFF, (IONIOFF) ratio, and fT. High KFIN brings up all the above parameters. While high KISO is preferred for better ION, IOFF, and (IONIOFF) performance, low KISO is improves fT. Moderate WFISO is suggested to improve (IONIOFF) ratio.