| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 7150365 | Solid-State Electronics | 2018 | 15 Pages |
Abstract
This paper reports the fabrication and electrical characterization of planar SOI Tunnel FETs (TFETs) made using a Low-Temperature (LT) process designed for 3D sequential integration. These proof-of-concept TFETs feature junctions obtained by Solid Phase Epitaxy Regrowth (SPER). Their electrical behavior is analyzed and compared to reference samples (regular process using High-Temperature junction formation, HT). Dual ID-VDS measurements verify that the TFET structures present Band-to-Band tunnelling (BTBT) carrier injection and not Schottky Barrier tunnelling. P-mode operating LT TFETs deliver an ON state current similar to that of the HT reference, opening the door towards optimized devices operating with very low threshold voltage VTH and low supply voltage VDD.
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Authors
C. Diaz Llorente, C. Le Royer, P. Batude, C. Fenouillet-Beranger, S. Martinie, C.-M.V. Lu, F. Allain, J.-P. Colinge, S. Cristoloveanu, G. Ghibaudo, M. Vinet,