Designing a 2-to-4 decoder on nanoscale based on quantum-dot cellular automata for energy dissipation improving

Quantum dot Cellular Automata (QCA) as a new architecture at the nanoscale is developed as a feasible alternative for the existing Complementary Metal-Oxide-Semiconductor (CMOS) designs. The decoder in the QCA is a very important circuit to address the QCA-based random access memory arrays. It plays a key role in many circuit designs, such as Controlled Logic Block (CLB), Field Programmable Gate Array (FPGA), and memory circuits' designs. In this paper, a five-input majority gate is used in a modular design methodology to design a 2-to-4 decoder in QCA. The proposed 2-to-4 QCA-based decoder can be utilized to synthesize n-to-2n decoders as well. The functional correctness of the proposed circuit is evaluated using QCADesigner tool. Also, QCAPro simulator as a popular power estimator tool in QCA evaluates the power dissipation. The obtained results have shown the significant success in terms of clock speed (%57), wire-crossing (%33), cell number (%27), area (%26) and power dissipation than the existing designs.