Effects of the post nitridation anneal temperature on performances of the nano MOSFET with ultra-thin (<2.5 nm) plasma nitrided gate dielectric

A post nitridation annealing (PNA) is used to improve performances of the metal oxide semiconductor field effect transistor (MOSFETs) with nano scale channel and pulsed radio frequency decoupled plasma nitrided ultra-thin (<50 Å) gate dielectric. Effects of the PNA temperature on the gate leakage and the device performances are investigated in details. For a n-type MOSFET, as the PNA temperature rises from 1000 to 1050 °C, the saturation current and gate leakage are increased and reduced 7.9% and 3.81%, respectively. For a p-type MOSFET, the improvement is more significant i.e., 16.7% and 4.31% in saturation current increase and gate leakage reduction, respectively. The significant improvements in performance are attributed to the higher PNA temperature caused Si/SiON interface improvement and increase of EOT. Most of all, the high temperature PNA does not degrade the gate oxide integrity.

► A PNA is used to improve performances of the nano MOSFET. ► The nano MOSFET has <50 Å DPN deposited SiON gate dielectric. ► PNA temperature under 1050 °C, Idsat is increased 7.9%/16.7% for n/pMOSFETs. ► PNA temperature under 1050 °C, Igi is reduced 3.81%/4.31% for n/pMOSFETs. ► The high temperature PNA does not degrade the gate oxide integrity.