Application of piezoresistive stress sensors in ultra thin device handling and characterization

Because of 3D integration, thickness of Silicon wafer is thinner and thinner. For thin silicon ICs, challenges in wafer thinning, handling and assembly process increase. The piezoresistive stress sensors studied in this paper are for experimental purpose, with which detailed stress can be measured during semiconductor process, e.g. wafer thinning. Almost seven times increase in stress have been observed when wafer thickness decreases from 400 μm to 100 μm. The advantages of these stress data are: (1) serve as a basis for process selection to meet the trends and needs of a reliable package, and for the development and improvement of existing processes; and (2) are important to enhance survivability during wafer thinning, handling and further processing. An ultra thin wafer handling method using support wafer has been investigated to handle 50 μm thick wafers. The process for the support wafer method has been well established, which is highly recommended to be used for all processes.